1. Field of the Invention
The present invention relates to a method of programming and/or verifying a nonvolatile memory, and particularly to a method of programming and/or verifying a threshold voltage of a nonvolatile memory.
2. Background of the Related Art
The packing density of a conventional nonvolatile memory corresponds in a one to one fashion to the number of memory cells. When nonvolatile semiconductor memory devices such as EEPROMs and flash EEPROMs are used as mass storage media, it is difficult to overcome the high cost-per-bit of the memories. To solve such a problem, a multibit cell stores data of over two bits in one memory cell to enhance the density of data on the same chip area without increasing the size of the memory cell. To achieve the storage of over two bits, more than two threshold voltage levels can be programmed on respective memory cells.
For example, in order to store data of two bits for every cell, the respective cells must be programmed in 2.sup.2 (four) threshold voltage levels. The four threshold voltage levels correspond to logic states 00, 01, 10, and 11, respectively. During the programming of the multiple levels, a problem arises due to a statistical distribution of the respective threshold voltage levels.
A typical distribution value is about 0.5 V. By precisely adjusting the respective threshold voltage levels, the voltage distribution can be reduced so that more voltage levels can be programmed, which increase the number of bits per cell. To adjust the threshold voltage levels in a conventional method, repeated programming and verification are performed. For programming, a series of voltage pulses are applied to the cells to adjust the threshold voltage levels. To verify whether a cell has reached an intended threshold voltage level, a read operation is performed between the respective programming voltage pulses. Programming is concluded when the verified threshold voltage level reaches the intended threshold voltage level.
In the conventional method of repeated programming and verification, there is difficulty in reducing the error distribution of the threshold voltage level due to the limited pulse width of a program voltage. Further, the algorithm of repeated programming and verification is implemented with additional circuits, increasing the area of peripheral circuits on the chip. The repetitive method also prolongs the programming time. To solve such problems, R. Cernea of SunDisk Co., Ltd. suggested a method of simultaneous programming and verification in U.S. Pat. No. 5,422,842.
FIG. 1A illustrates the symbol and circuit diagram of the electrically writable nonvolatile memory. The nonvolatile memory cell includes a control gate 1, a floating gate 2, a source 3, a channel area 4, and a drain 5. When voltages sufficient to cause programming are applied to control gate 1 and drain 5, a current flows between drain 5 and source 3, and electrons are injected into the floating gate 2. This current is compared to a reference current, which varies for each threshold voltage level to be programmed. When the current reaches a value equal to or smaller than the reference current, a programming completion signal is produced. The auto verification of a programmed condition at the same time as programming may compensate for the disadvantage of the repetitive program verification.
However, as disclosed in U.S. Pat. No. 5,043,940, the reference current varies for each of the threshold voltage levels to be programmed during the multi-level programming method. As shown in FIG. 1B, the relationship between the reference currents and the cell threshold voltages is neither explicit nor linear. Therefore, a current controlled type programming method like that in the aforementioned prior art has a disadvantage that a direct and effective multi-level control cannot be easily implemented.
The above references are incorporated by reference herein where appropriate for appropriate teachings of additional or alternative details, features and/or technical background.